1. Field of the Invention
This invention relates to microelectronic devices and related fabrication methods. More particularly, the invention relates to microelectronic vertical field effect transistors and related fabrication methods.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. Conventional semiconductor electronic storage devices, such as Dynamic Random Access Memory (DRAM), typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection.
A dynamic random access memory cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device, such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET, or simply FET). These access devices function to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the electrode (or storage node) area and the interelectrode spacing. The conditions of DRAM operation such as operating voltage, leakage rate and refresh rate, will generally mandate that a certain minimum charge be stored by the capacitor.
FETs are widely used in integrated circuit devices including logic, memory and/or microprocessor devices that are used in consumer and/or industrial applications. For example, FETs are commonly used as the access device for DRAM memories. As the integration density of integrated circuit FETs continues to increase, it may be desirable to continue to shrink the dimensions of the FETs. Conventionally, features of integrated circuit FETs may be formed on a microelectronic substrate, such as silicon semiconductor substrate, using photolithography and etching. Unfortunately, as the minimum feature size scales into the sub-0.1 micron region, it may be increasingly difficult to define such small features using traditional lithography and etching. Although improved nano-lithography techniques may be developed, it still may be difficult to reliably define features as small as 35 nm or smaller in a controllable and cost-effective way using lithography, to allow mass production.
In order to increase efficiency of memory devices, there is a similar effort to create smaller memory cells. DRAM memory cells can shrink in several ways. One way to decrease the size of a memory cell is to reduce the minimum feature size (F). This generally occurs through new and advanced lithography and etching techniques. Memory cells can also be decreased by designing a smaller memory cell. For example many of the DRAM chips on the market today have a memory cell size of 8F2 or greater, where F is the dimension of the minimum feature for a given manufacturing process. However, as the size of FETs and memory cells continue to decrease, there is an increase in the electrostatic charge sharing between gate and source-drain regions of the transistor devices. This electrostatic charge sharing is typically referred to as the short channel effect. As those of skill in the art readily recognize, as the length of the transistor channel decreases, the threshold voltage of the transistor also increases due to the short channel effect. Thus, there is a need for improved systems and methods of reducing the size of memory devices, while reducing the short channel effect on the reduced size memory devices.